programming
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Table of Contents
Programming
C
- With GCC one can do inline functions (useful with microcontrollers). http://gcc.gnu.org/onlinedocs/gcc-4.4.0/gcc/Inline.html#Inline . Useful gcc command line: -Winline
- GCC_EXEC_PREFIX . For defining the GCC executables prefix
Makefiles
- Targets without prerequisites are called phony targets (clean target)
- Is standard practice to have an OBJS(or objects) variable to list all the object files.
- There is an implicit rule to make .o files out of .c files: example.o: example.h
- If you have several target depending of the same (not .c) prerequisites you can do: kbd.o command.o files.o : command.h
- A good clean rule. .PHONY tell explicitly that clean is a phony target (in case there is a file called “clean” in the directory). With -rm execution continues even with errors coming out of rm. Ex:
.PHONY : clean clean : -rm edit $(objects)
- Variables are used with $()
- “-” in front of a shell commands ignores errors.
- MAKEFILES is an environmental variable that tells make to include the makefiles listed there if they exist. Used in recursive invocations of make.
- It seems that Double-colon rules (::) are always executed (updated)
- make -n target will print the commands to update target without executing them. make -s silences echoing.
- $? only files that have change from the list of prerequisites of a rule.
- $^ list of all the prerequisites of a rule.
- $@ target
- $< is only the first prerequisite. Useful when you have also header files as prerequisites but you don't want to put them on the compilation commands.
- A prerequisite can be of the form: -lname. It will look for a file called libname.so and then libname.a
- Wildcards only get automatically expanded in rules for the rest use: $(wildcard pattern…)
- Substitution: $(patsubst %.c,%.o,$(wildcard *.c))
- VPATH contains the search directories. vpath Directive is a search path for files under a pattern
vpath %.h ../headers
- CFLAGS variable is use during the c implicit rule compilation.
- make -C dir specifies the working directory.
- See the phony section in the manual for multiple directory makefiles, and parallel processing
- Trick to generate several programs in the same directory:
all : prog1 prog2 prog3 .PHONY : all ... rules for programs
- extradeps= takes the argument from make extradeps=foo
- $(objects): %.o: %.c Static Pattern rules. One can specify to which target is applies, you can't with implicit rules. It overwrites implicit rules.
- $(filter %.o,$(files)) filters all .o files out of $files
- $* expands to what is in % (the stem)
- When a target appears in more than one rule the rules must be of the same type (: or ::)
- When a target appears in more that one :: rule, the rules executed are the ones where the target is older than the prerequisites.
- cc -MM main.c gives main.o : main.c defs.h
- For each source file name.c there is a makefile name.d which lists what files the object file name.o depends on.
- Here is the pattern rule to generate a file of prerequisites (i.e., a makefile) called name.d from a C source file called name.c:
%.d: %.c @set -e; rm -f $@; \ $(CC) -MM $(CPPFLAGS) $< > $@.$$$$; \ sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \ rm -f $@.$$$$
- $(sources:.c=.d) substitutes from sources all .c files to .d files
- @ disables echoing in the shell commands area.
- For command execution each line gets executed with a separated shell. Be careful with “cd”. Put it in the same line with the next command with “;”
- Check “&&” shell operator, useful for stopping executing if the prior command gave an error.
- make -j . Gives parallel processing.
- make -i . Ignores all errors.
- If a target fails the right thing to do is to erase the target file. Check here why. make will do this if .DELETE_ON_ERROR appears as a target.
- Recursive make:
subsystem: cd subdir && $(MAKE)
- Use $(MAKE) instead of make
- You can export variables to the sub-make with “export variable”
programming.1245378825.txt.gz · Last modified: 2021/02/01 05:55 (external edit)