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--- stm32 [2009/06/14 13:34] – memeruiz
+++ stm32 [2021/02/01 05:55] (current) – external edit 127.0.0.1
@@ Line 33: / Line 33: @@
   * table 5 of stm32_low_medium_high summarizes the boot pins.
   * There is an embedded boot loader in system memory for usart1 programming
+===== Power control, Clock and Reset=====
+  * Voltage detector is enabled in PVDE bit in PWR_CR
+  * For slowing down CPU speed take a look in RCC_CFGR
+  * Enabling disabling peripherals in : RCC_APB1ENR RCC_APB2ENR and RCC_AHBENR
+  * For entering sleep mode use WFI (wait for interrupt) or WFE (wait for event) instruction. SLEEPONEXIT (Cortex system control register) is important to select the way entering sleep workds. Wake on event is faster because is not entering any interrupt rutine.
+  * Stop mode table 10 stm32_low_medium_high. The internal regulator can be set in low_power mode with LPDS bit in PWR_CR.
+  * Reset origin (reason for the reset, what produced the reset) can be check in RCC_CSR. There is software reset.
+  * System clock SYSCLK can be driven by HSI, HSE, PLL clocks
+  * For clock configuration check RCC_CR.
+  * One can check if HSI (8MHz internal RC osc) is stable with the HSIRDY flag
+  * The PLL can multiple HSI and HSE. Configuration of PLL must be done before enabling it. And interrupt can be generated when the PLL is ready.
+  * The LSI internal RTC source can be calibrated to get Real time like behaviour. Pag 71 stm32_low_medium_high
+  * After reset HSI is selected as system clock (SYSCLK). Clock source must be ready to be selected as new clock, check RCC_CR flags for that. With CSS (clock security system) the system detects a failure in the HSE and changes automatically to HSI and issues a NMI.
+  * The stm32 can output 4 different types of clock in MCO pin. RCC_CFGR
 ===== Peripherals =====
   * Before using them they have to be enabled in RCC_AHBENR RCC_APB1ENR RCC_APB2ENR
+===== GPIO =====
+  * Each GPIO port has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR).
+  * GPIO registers must be accessed as 32bits words
+  * GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses. Ints are not affecting then.
+===== Interrupts =====
+  * 60 interrupt lines + 16 Cortex interrupts. 16 programmable priority levels.
+===== Watchdogs =====
+  * Apparently watchdogs are disabled after reset by default
+===== Device electronic signature =====
+  * The size of the memories contained in the stm are stored in the system memory in some special registers. This may be used by the compiler and/or by the programmer.
+  * Device ID. (serial number)
+===== Setup order =====
+  - Disable Interrupts?
+  - Configure clocks RCC_CR RCC_CFGR
+  - Configure power PWR_CR
+  - Configure GPIOs GPIOx_CRL/H
+  - Set output GPIO pins to non problematic values GPIOx_ODR or GPIOx_BSRR/BRR
+  - Configure Peripherals
+  - Configure Interrupts
+===== ARM CORE =====
+  * You can write to the PSR, APSR, IPSR, EPSR using the MSR instruction. In fact is possible make combinations of this registers.