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stm32 [2009/06/14 16:15] – memeruizstm32 [2021/02/01 05:55] (current) – external edit 127.0.0.1
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   * For entering sleep mode use WFI (wait for interrupt) or WFE (wait for event) instruction. SLEEPONEXIT (Cortex system control register) is important to select the way entering sleep workds. Wake on event is faster because is not entering any interrupt rutine.   * For entering sleep mode use WFI (wait for interrupt) or WFE (wait for event) instruction. SLEEPONEXIT (Cortex system control register) is important to select the way entering sleep workds. Wake on event is faster because is not entering any interrupt rutine.
   * Stop mode table 10 stm32_low_medium_high. The internal regulator can be set in low_power mode with LPDS bit in PWR_CR.   * Stop mode table 10 stm32_low_medium_high. The internal regulator can be set in low_power mode with LPDS bit in PWR_CR.
-  * Reset origin can be check in RCC_CSR. There is software reset.+  * Reset origin (reason for the reset, what produced the reset) can be check in RCC_CSR. There is software reset.
   * System clock SYSCLK can be driven by HSI, HSE, PLL clocks   * System clock SYSCLK can be driven by HSI, HSE, PLL clocks
   * For clock configuration check RCC_CR.   * For clock configuration check RCC_CR.
Line 51: Line 51:
 ===== Peripherals ===== ===== Peripherals =====
   * Before using them they have to be enabled in RCC_AHBENR RCC_APB1ENR RCC_APB2ENR   * Before using them they have to be enabled in RCC_AHBENR RCC_APB1ENR RCC_APB2ENR
 + 
 ===== GPIO ===== ===== GPIO =====
-  * Each GPIO port has two 32-bit configuration registers (GPIOx_CRL, +  * Each GPIO port has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR).
-GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset +
-register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register +
-(GPIOx_LCKR).+
   * GPIO registers must be accessed as 32bits words   * GPIO registers must be accessed as 32bits words
   * GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses. Ints are not affecting then.   * GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses. Ints are not affecting then.
 +
 +===== Interrupts =====
 +
 +  * 60 interrupt lines + 16 Cortex interrupts. 16 programmable priority levels.
 +
 +===== Watchdogs =====
 +  * Apparently watchdogs are disabled after reset by default
 +
 +===== Device electronic signature =====
 +
 +  * The size of the memories contained in the stm are stored in the system memory in some special registers. This may be used by the compiler and/or by the programmer.
 +  * Device ID. (serial number)
 +
 +
 +
  
 ===== Setup order ===== ===== Setup order =====
Line 69: Line 81:
   - Configure Peripherals   - Configure Peripherals
   - Configure Interrupts   - Configure Interrupts
 +===== ARM CORE =====
 +
 +  * You can write to the PSR, APSR, IPSR, EPSR using the MSR instruction. In fact is possible make combinations of this registers. 
  
  
stm32.1244996109.txt.gz · Last modified: 2021/02/01 05:55 (external edit)